a) Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a highly integrated semiconductor device having fine patterns and its manufacturing method.
b) Description of the Related Art
As the integration density of semiconductor integrated circuit devices increases the wiring patterns (inclusive or electrode patterns) are made finer and highly integrated. In order to form intersecting wiring patterns, it is necessary to form a plurality of wiring layers with interlevel or interlayer insulating films being interposed therebetween. In order to form multi-layered wiring patterns, it is necessary to perform photolithography for forming contact holes in insulating layers and for patterning wiring layers.
The following methods (A) to (D) are known as the methods of patterning a wiring or electrode conductive material layer.
(A) As shown in FIG. 32, a conductive material layer 3 is formed on an insulating film 2 covering the surface of a semiconductor substrate 1. A resist film is coated on the conductive material layer 3, and resist patterns 4A to 4C having a desired shape are patterned therefrom by photolithography in a well-known way. By using these resist patterns as a mask, the conductive material layer 3 is selectively dry-etched.
(B) As a patterning mask, a silicon oxide film or silicon nitride having a low etching rate is used (for example, refer to Japanese Patent Laid-open Publication No.2-125425). Also used as a patterning mask for patterning a polysilicon layer is a laminate of a silicon oxide or silicon nitride film and a resist layer formed thereon (for example, refer to J. S. Maa et al.: J. Vac. Sci. Technol. B9(3), May/June, 1991, pp.1596-1597).
(C) In coating a resist mask on a high reflectivity substrate, a resist layer mixed with light-absorbing dye is used.
(D) In patterning a conductive material layer formed on a high reflectivity substrate, an antireflection film is coated on the surface of the conductive material layer. As an antireflection film, a silicon nitride film is used (for example, refer to Japanese Patent Laid-open Publications Nos.1-241125 and 5-55130) or a RiN film is used (for example, refer to Japanese Patent Laid-open Publications Nos.60-240127, 61-185928, and 63-232423).
A laminate structure of a barrier metal layer, an aluminum layer and an anti-reflection layer such as TiN or amorphous silicon is etched by using resist patterns as a sole mask (P. E. Riley et al.: Solid State Technology February, 1999, pp.47-55).
When a fine wiring pattern is formed by the method (A), there occurs a phenomenon (the microloading effects of an etching rate) that an etching rate changes with a wiring space (space width).
As shown in FIG. 32, in the case of patterns reducing space widths between adjacent pairs of the resist patterns 4A, 4B, 4C, . . . , the etching rate may become lower as the space width is narrowed as shown in FIG. 33. If the conductive material layer is etched to a predetermined depth at the narrow space width, the layer at the broad space width may be etched excessively and the underlie layer such as the insulating film 2 may be thinned.
In some cases, an etching rate is increased as the space width is narrowed. As shown in FIG. 34, in the case of patterns increasing space widths between adjacent pairs of resist patterns 4a, 4b, 4c, 4d, . . . , the etching rate may be increased as the space width is narrowed as shown in FIG. 35. Therefore, if a conductive material layer 3 is etched to a predetermined depth at the broad space width, the layer at the narrow space width may be etched excessively, and if a selective etching ratio of the underlie layer is low, the underlie layer may be etched as indicated at X.sub.1 and X.sub.2.
When a fine wiring pattern is formed, there occurs a phenomenon (the microloading effects of a shape of an etched layer) that a shape or size of an etched layer change with the space width. Such a size change lowers a yield of forming wiring patterns.
Specifically, as shown in FIG. 36, if densely distributed wiring patterns 3P and 3Q are formed by dry etching by using densely distributed resist patterns 4P and 4Q, the width W.sub.D of the densely distributed wiring pattern 3P for example may become nearly equal to the width W.sub.O of the resist pattern 4P (W.sub.D .apprxeq.W.sub.O). In contrast, as shown in FIG. 37, if an isolated wiring pattern 3R is formed by the same dry etching by using an isolated resist pattern 4R, generally the width W.sub.I of the isolated wiring pattern 3R becomes broader than the width W.sub.D shown in FIG. 36 (W.sub.I &gt;W.sub.D). For the etching of a laminated layer of WSi.sub.2 /polycrystalline silicon, the width exceptionally becomes W.sub.I &lt;W.sub.D.
In forming fine wiring patterns, the amount of thinning a film of mask material such as resist increases and the etching selectivity of the mask material (etching ratio of the layer to be etched with respect to the mask) lowers. There is therefore a tendency of lowering a yield of forming wiring patterns.
A film of mask material is thinned during dry etching by collisions of ions or particles having high kinetic energy with the mask material as well as the chemical reaction between gas and the mask material. Collisions of particles having high kinetic energy with the mask material truncate the shoulders of a resist film 4S as shown in FIG. 38. The angle of each mask material shoulder takes a value giving the best sputtering efficiency. A real angle is not 45.degree. which gives the best efficiency in purely physical etching. The phenomenon of truncating the shoulders of mask material is called "faceting", and the plane formed at each shoulder is called a "facet". FIG. 39 shows a state where two opposing facets meet each other.
FIG. 38 illustrates a process of forming a wiring layer by dry-etching a conductive material layer 3 by using the resist layer 4S as a mask. A line width (wiring pattern width) K is set to have a small value approximately equal to the thickness T of the conductive material layer 3. Even if faceting occurs as shown in FIG. 38, the top surface of the resist layer 4S is left until the right and left facets meet each other. In this case, the amount T1 of thinning a resist film is equal to that of a resist pattern having a sufficiently large area as compared with the thickness T of the conductive layer 3 to be etched. The sufficiently large area means a large dimension in any in-plane direction of a resist pattern.
This phenomenon becomes more conspicuous as the width of a wiring pattern becomes small. That is to say, an effective selectivity of the wiring pattern to resist lowers more as the wiring pattern becomes narrower.
FIG. 40 shows a dependency upon a line width K of an amount of thinning a resist film, a selection ratio with respect to the resist film, and a resist taper angle .theta.. As shown in FIG. 40, the resist taper angle .theta. is an angle between a line extended from a facet and a bottom surface of the conductive material layer 3. Data shown in FIG. 40 were obtained when aluminum alloy was etched by using BCl.sub.3 /Cl.sub.2 as an etchant gas and a microwave plasma etcher to be described later with reference to FIG. 16. The data shows that as the line width K becomes narrow, the amount of thinning a resist film increases (the selection ratio of the conductive material to resist lowers) and the resist taper angle .theta. becomes large.
Although a resist mask used as an etching mask is preferably made thin, a substantial selection ratio wiring patterns with respect to an etching mask lowers as wiring patterns are made fine, as previously described with references to FIGS. 38 to 40. As a result, if a resist layer is made thin, the resist mask may be etched completely during etching and wiring patterns may be broken.
In order to prevent a selection ratio from being lowered as patterns are made fine, it is necessary to develop etching techniques having a high selection ratio with respect to mask material or to use mask material providing a high selection ratio. The method (B) is effective for raising a selection ratio with respect to mask material.
However, if a silicon oxide film is used as a patterning mask, this mask is associated with a problem that it rarely has a function as an antireflection film. A silicon nitride film used as a patterning mask has an insufficient antireflection function. With either method, inorganic mask material is left on the surface of a wiring pattern or an electrode after etching. If the substrate is exposed to a high temperature at a later process, the mask material may be peeled off from the surface of the wiring pattern or electrode to produce mask material particles, because of a difference of thermal expansion coefficients between mask material and conductive wiring material. Therefore, a yield is lowered. Such a phenomenon occurs at a heat treatment such as a lamp annealing process for activating impurities ion-implanted into source/drain regions and a CVD process for forming an interlevel or interlayer insulating film at a temperature of 400 to 500.degree. C.
Another problems associated with the formation of a wiring pattern on a high reflectivity substrate is that a pattern size precision is lowered by light reflections at the substrate surface.
Specifically, suppose a situation as shown in FIG. 41. Insulating films 5A and 5B are formed on the surface of a semiconductor substrate 1, forming a step on the substrate surface. A resist layer 7A is formed over the substrate surface on a wiring material layer 6A. Light 9 is irradiated to the resist layer 7A at the exposure process through a mask 8 having a desired pattern. Light is reflected in a direction different from the incident direction at sloped surfaces A-B and C-D of the high reflectivity wiring material layer 6A, and is incident upon the regions of the resist layer 7A not to be exposed. The regions not to be exposed are applied with light. Thereafter, the resist development process is performed. FIG. 42 is a plan view of the etched resist pattern, and FIGS. 43 and 44 are cross sectional views taken along lines X-X' and Y-Y' of FIG. 42, respectively. A resist pattern 7 with a narrow part such as shown in FIG. 42 is formed.
At the flat region, the cross section of the resist pattern 7 is rectangular and has a designed width W.sub.1 as shown in FIG. 43. At the region surrounded by the insulating films 5A and 5B, the cross section of the resist pattern 7 is semicircular and has a narrower width W.sub.2 than the designed width W1, as shown in FIGS. 42 and 44. Therefore, as the wiring material layer 6A is dry-etched by using the resist layer 7 as a mask, the obtained wiring layer has a narrowed part the portion of width W.sub.2 or is broken at this portion.
Still another problem associated with the formation of a wiring pattern on a high reflectivity substrate is that a pattern size changes at the regions having different reflectivities.
For example, as shown in FIG. 45, an insulating film 11 is formed over a substrate 1, covering an insulating film 5 and polycide gate electrode layer 10. Thereafter, a contact hole 11a reaching the substrate surface and a contact hole 11b reaching the polycide gate electrode layer 10 are formed in the insulating film 11 by dry etching using the resist layer 12 as a mask. In this case, the size W.sub.A of the contact hole 11a becomes smaller than the size W.sub.B of the contact hole 11b. The larger size of the contact hole 11b reduces an alignment margin at the photolithography process. As shown in FIG. 46, in some cases the contact hole 11b may be off-set from the position of the polycide gate electrode layer 10. Side wall oxide of the gate electrode is etched at an oxide etching process. The gate wiring interconnects the gate electrode and source/drain region. In order to avoid such a case, it is necessary to use a large alignment margin at the design stage, and so the integration density should be lowered.
A large size of a contact hole at a high reflectivity region may result from the phenomenon that the diameter R of the contact hole in the resist layer 12 becomes large. The reason of the phenomenon that the diameter R becomes large will be explained in the following.
In photolithography techniques, photosensitive material which makes resist hard to be soluble in development liquid, is decomposed only at the region exposed to light to make the resist easy to be soluble in the development liquid. A resist pattern is formed by selectively dissolving the resist. The photosensitive material is decomposed more as the exposure energy is increased. Therefore, the diameter R of the contact hole shown in FIG. 47 becomes larger as the exposure energy is increased.
Since the polycide gate electrode layer 10 having a high reflectivity exists under the resist layer 12, light reflected by this high reflectivity material is applied to the resist layer 12. Therefore, the effective exposure energy absorbed by the resist layer 12 becomes larger than at the region having a low reflectivity. As a result, decomposition of the photosensitive is enhanced and the diameter R of a contact hole becomes large.
The method (C) uses a resist layer mixed with dye which absorbs exposure light. Therefore, reflection at the lower level layer is reduced so that the size precision to be degraded by light reflection can be suppressed to some degree.
However, as shown in FIG. 48, even if a resist layer 15 containing dye is formed to have a desired pattern, on a wiring layer 14 covering an insulating film 5, the cross section of the resist layer 15 has a tapered skirt. This is because the exposure energy in resist is attenuated toward a deeper region from the surface thereof, and the region not exposed is left unetched. The size of a resist pattern becomes large as the exposure energy becomes small. A pattern width is generally and often defined by the bottom of a resist pattern. Therefore, a pattern is designed on the assumption that a skirt is formed. The skirt portions a and b of the resist layer 15 are etched when the wiring material layer 14 is dry-etched to form wiring patterns. Therefore, the wiring layer may be thinned. The resist layer 15 containing dye lowers a resolution of photolithography. It can be said therefore that the method (D) is not suitable for fine patterns.
The method (D) suppresses light reflection by forming an antireflection film on the surface of a conductive material layer under a resist layer. Therefore, this method is effective for preventing a size precision from being degraded by light reflection, and does not have the problem associated with the method (C).
Although the method (D) uses an antireflection film, a sufficiently thick resist layer is used as an etching mask so that the microloading effects during dry etching cannot be reduced.
Photolithography techniques for patterning a conductive material layer have been explained above. Similar photolithography techniques are also used for forming a contact hole or a recess in an insulating film.
A reflectivity of the surface of an insulating film is considerably small as compared to that of the surface of a conductive material layer. An insulator such as silicon oxide is transparent relative to ultraviolet rays and allows incident light to reach the surface of the underlie layer. If a high reflectivity surface such as metal and semiconductor exists under an insulating layer, a pattern precision is also degraded by reflected light beams and the microloading effects also occur.